This invention relates to dynamic memory systems, and is more particularly directed to an improved transparent refreshing system for large capacity dynamic memory chips.
It is well known that dynamic memory chips must be periodically refreshed, in order that the data stored therein may be retained. While a refreshing action occurs when the chips are addressed, for read or write cycles, the retention of the data in the memories cannot depend upon such addressing, since the operations may not occur with sufficient rapidity to reliably insure the refreshing. For example, on a type 4116 dynamic chip, which has a capacity of 16 K, the entire chip must be refreshed at least once every two milliseconds.
It is of course undesirable to require refreshing at times that would interfere with the normal operation of a data processing system, and hence it is desirable to render the refreshing transparent to the system, for example, by refreshing at times when the memory could not be addressed.